In the past, there have existed various synchronization methods and the corresponding reception units. They have been used, inter alia, in fieldbus systems, for example the PROFIBUS. Such fieldbus systems are distributed control systems which generally have a transmission unit (head assembly, bus master) and a multiplicity of reception units (slaves). The individual slave assemblies are usually driven by virtue of the transmission unit transmitting an instruction message to the reception units. Upon receipt of the instruction message, the reception units output nominal values to a controlled technical installation which have been transmitted to them previously by the transmission unit. At the same time, they read in from the controlled technical installation actual values which they subsequently transmit to the transmission unit. The transmission unit then calculates new nominal values which it transmits to the individual reception units, so that the reception units are ready for the next instruction message.
The instruction messages are sent by the transmission unit with equidistant timing. From the instruction messages it is therefore possible to derive synchronization signals which can be used to synchronize the reception units to the transmission unit.
In practice, there is a time delay between transmission of the actual values read into the transmission unit and transmission of the nominal values to the reception units, on the one hand, and transmission of the next instruction message, on the other hand. This delay is generally used for “acyclic” messages. In this context, delays by the acyclic messages may cause individual instruction messages to be sent late. Reception of such delayed instruction messages may cause erroneous resynchronization of the reception units. In some applications, this erroneous resynchronization is not critical. However, in time-critical applications, erroneous resynchronization may be crucial. In time-critical applications, particularly when coupling interpolating drive axes, erroneous resynchronization cannot be tolerated.
For example, in German Patent Application DE 19932635.5 a PI controller as a phase regulator has been used to achieve sufficient accuracy in the synchronization with the transmission unit.
The phase regulator in a phase-locked loop (PLL) generates a stable clock signal essentially from a synchronization signal which is received via the fieldbus system and is subject to interference.
However, because of quartz drifting, the period length of the clock signal on the fieldbus system may deviate from the period length expected from the point of view of the PLL for the clock signal. The PLL must therefore continue to provide its own generated clock signals with corrections so that it remains synchronous with the synchronization signal of the transmission unit.
The synchronization signal is, moreover, subdivided by means of the PLL into a fixed number of high-frequency subordinate clock pulses. These subordinate clock pulses are generated with a set period length. However, in order to ensure synchronicity of these subordinate clock pulses with the superordinate synchronization signal, the correction determined by the PLL, which is essentially determined by the effects of the quartz drifts, is conventionally corrected, for the sake of simplicity, completely in the first of these subordinate clock pulses, depending on the synchronization signal. This results in a pulsating clock pattern in the case of the subordinate clock signals.
An example of the conventional mode of the resynchronization procedure is shown in FIG. 4 with the aid of a timing diagram in which the synchronization signal S and the subordinate clock signal u are plotted against time t. The synchronization signal S is expected in this case to be longer than that from the PLL. The subordinate clock signal u is generated by a multiple frequency n, from which intervals a result. In this case, a describes the nominal period of the subordinate clock signal u. Only the first interval a of the n subordinate clock signals in the example is correspondingly lengthened by a required correction value A1 of the phase regulator. It holds in this case that: A1>0.
FIG. 5, which has the same design in principle, shows the case when the synchronization signal S is shorter than that from the PLL. Then, only the first interval a of the n subordinate clock signals u in the example are correspondingly shortened by required correction value A2 of the phase regulator. It holds in this case that: A2<0.
In the case of time-critical applications, by contrast, particularly the coupling of interpolating drive axes already mentioned, this result with pulsating clock patterns is undesirable. The accuracy or precision of axes which are interpolating with respect to one another and are operated synchronously, for example in numerically controlled machine tools or robots, depends on the accuracy of the generated clock pulses.
In order to achieve the highest possible accuracy, it is necessary that the subordinate clock signals u be equidistant from one another exactly as are the synchronization signals S. Such an advantageous result is shown with the aid of FIG. 6, which illustrates the same signals which are shown in FIGS. 4 and 5, but now with equidistant intervals a*, which deviate from the nominal period length a, as a rule.
In many applications, the subordinate clock signals constitute, for example, the current regulator clock of drives. In this case, equidistant clock pulses have a direct effect on the “running smoothness” of the drives.
Accordingly, there remains a need for a method of synchronizing the clock pulses from a clock generator and the synchronization signals from reception units. It is, therefore, the object of the present invention to develop a synchronization method such that reception units can generate equidistant subordinate clock pulses.